**Shifting Registers**

**Registers** are sets of ** Edge Triggered Latches** (

**ETL**) working together with the groups of bits that we have been referring to.

The amount of ** ETL** in a

**is related to the width of the**

*Register***, the internal temporary memories of a CPU. They will have 8, 16, 32 or 64**

*CPU Registers***each if the CPU has 8, 16, 32 or 64 bits of processing ability, respectively. It’s this width that defines the number of**

*ETL***to be placed in the**

*ETL***for all the Registers.**

*CPU circuitry,*According to the ** ETL** they integrate, they can be

**sensible**

*Clock Rising Edge***or**

*Registers*

*Clock***sensible**

*Falling Edge***.**

*Registers*Sometimes it is necessary to ** shift** the bits from one register to either the

**or to the**

*left***.**

*right*Specifically, when performing a multiplication and/or division with iterations, with each iteration corresponding to a shift of the operating digit to the left or right. Shifting a number one bit to the left is equivalent to multiplying it by 2. Shifting a number one bit to the right is equivalent to dividing it by 2.

A common use of ** Shift Registers** is the conversion of parallel streams (one complete bus, ex. 8 bits, at the same time) to serial transmission (one by one). The 8 bits are fed to the outputs of the shift register and a set of eight shifts is initiated. For each shift, one bit goes out to the serial transmission line. When finished, a new set of 8 bits is fed to the outputs of the

**and a new conversion begins. The same thing applies to the reverse process.**

*Shift Register,*For each ** left shift,** one bit leaves to the left and one new bit comes in from the right. Each bit occupies the spot immediately at its left. For each

**one bit leaves to the right and one new bit comes in from the left. Each bit occupies the spot immediately at its right. If there isn’t a bit ready to get in at each shift, by default, the value of the new bit will be**

*right shift,***0**.

The **Shift Register**, as any Register, consists of a set of ** ETL** (

*Edge Triggered Latches*), as many as the bit width of the CPU registers. For the

**Shift Register,**the ETLs are sequentially linked to each other, meaning, one’s input comes from the other’s output.

*And why are the registers ETL linked together?*

Like we said, every bit will take up the spot of another, either to the left or to the right. So the ETL will be linked in different manners, depending on the type of shift. But, one’s input will always be the next one’s left or right output.

The ETL assures us that any value getting to its inputs after the ** Clock Rising Edge** will always be memorized only on the next

**. After each bit is shifted, we’ll have to**

*Rising Edge**. For this to be possible, as we’ve seen in*

**freeze the shifted group of bits in order to process it****, we’ll have to use ETL. Once again, the influence of Clocked Logic in any operation becomes evident. Here, it’s responsible for synchronizing the Clock with the Shifts.**

*Clocked Logic***o**

*Only***.**

*ne shift per clock cycle**We are now using the word ***Memorize*** to refer to a value going from the input of a ETL to its output, and we must get used to this designation, because it’s what it means. The value is memorized at the ETL (kept in its output).*

**Right Bit Shifting**

In ** Figure 1** we’ve represented a

**Right Shift Register**with 2 bits width.

**is the ETL for the bit of order**

*B1***1,**and

**is the ETL for the bit of order**

*B0***0**.

- The bit
is prepared to go into*D*.*B1* - Output of
is connected to the input of*B1**B0*→*(B1*.*B0)* - Output of
is the bit*B0*going out of the circuit.*X,* - Both
and*A*are at the inputs*S*and*B1*.*B0*

When the ** clock rises**:

- Both
and*A*are memorized at*S*and*B1*, which is represented here by the*B0***cyan lines with the number 1**. is now at the input of*A*,*B0*through theconnection and*B1→B0*is now at the input of*D*, which is represented here by the*B1***orange lines with the number 2**.- The bits at
changed from SX*B1 B0*__,__to A S. - At the
(not shown):*next clock* - Both
and*D*are memorized in*A*–*B1, B0***cyan lines**. goes out through the*B***orange arrow**.- The bits at
change from*B1B0***A**,**S**to**D**,**A**.

The global evolution in **B1B0** was (left→right):

DA→SX D→AS→X DA→SX

**Left Bit Shifting**

In ** Figure 2** we represented a

**Left Shift Register**with 2 bits width.

**and**

*B1***are the same as before.**

*B2*the new bit, is at the input of*D,*.*B0*the leaving bit, is at the outup of*X,*.*B1*- The output of
is connected to the input of*B0**B1*.*(B0→B1)*

This is what is different about this circuit, when compared to the previous one. The remainder of its functionality is the same the above description, only in reverse. However, it would be an interesting learning exercise if you were to try and deduce the steps by yourself.

The global evolution in B1B0 was (right→left):

XA←SD X←AS←D XA←SD

In the global evolution showed for both the circuits, the shaded letters mean:

- Rose – Bits coming in.
- Blue – Bits that are leaving.
- Yellow – Bits being memorized.

**Shift Verification**

In ** Figure 3,** we analyzed the behavior of two Shift Registers with 4 bit width, with a simplified representation, over several Clocks.

Notice that the bits released by the ** Left Shift** in

**are those that are received by the**

*Frames I to V***in**

*Right Shift***and vice versa. This way, we form a closed circuit, ex. two**

*Frames VI to X***following each other.**

*left and right shifts*- The
**blue arrows**represent The ETL connections, and their direction. - The
**orange arrows**represent the circuit inputs and outputs, and their direction. - The dashed
**violet arrows**represent the memorization of the values in each ETL (input→output), under the effect of the.*Clock Rising Edge*

**Left Shift**

** Frame I** – Represents the initial situation of the

**with the**

*Left Shift Register,***at low. W,X,Y,Z in B3,B2,B1,B0 are the bits to be shifted.**

*Clock*- The bit
is at the input of*A*, and is the one being admitted.*B0* - The connections of the ETL are
→*B0*→*B1,B1*→*B2,B2**B3.* releases the bit*B3*.*W*

** Frame II** –

*1st***.**

*Clock*is released by*W*and is going to Frame VII.*B3*is admitted by*A*, coming from Frame VII.*B0*- The bits in B3,B2,B1,B0 are now X,Y,Z,A.

** Frame III** –

**.**

*2nd Clock*is released by*X*and is going to Frame VIII.*B3*is admitted by*B*, coming from Frame VIII.*B0*- The bits in B3,B2,B1,B0 are now Y,Z,A,B.

** Frame IV** –

**.**

*3rd Clock*is released by*Y*and is going to Frame IX.*B3*is admitted by*D*, coming from Frame IX.*B0*- The bits in B3,B2,B1,B0 are now Z,A,B,D.

** Frame V** –

**.**

*4th Clock*is released by*Z*and is going to Frame X.*B3*is admitted by*E*, coming from Frame X.*B0*- The bits in B3,B2,B1,B0 are now A,B,D,E.

**Right Shift**

** Frame VI** – Represents the initial situation of the

**with the**

*Right Shift Register,***at low. E,D,B,A in B3,B2,B1,B0 are the bits to be shifted.**

*Clock*- The bit
is at the input of*W*, and is the one being admitted.*B3* - The connections of the ETL are
→*B3*→*B2,B2*→*B1,B1**B0* releases the bit*B0*.*A*

** Frame VII** –

*1st***.**

*Clock*is released by*A*and is going to Frame II.*B0*is admitted by*W*, coming from Frame II.*B3*- The bits in B3,B2,B1,B0 are now W,E,D,B.

** Frame VIII** –

**.**

*2nd Clock*is released by*B*and is going to Frame III.*B0*is admitted by*X*, coming from Frame III.*B3*- The bits in B3,B2,B1,B0 are now X,W,E,D.

** Frame IX** –

**.**

*3rd Clock*is released by*D*and is going to Frame IV.*B0*is admitted by*Y*, coming from Frame IV.*B3*- The bits in B3,B2,B1,B0 are now Y,X,W,E.

** Frame X** –

**.**

*4th Clock*is released by*E*and is going to Frame V.*B0*is admitted by*Z*, coming from Frame V.*B3*- The bits in B3,B2,B1,B0 are now Z,Y,X,W.

*Did you notice anything curious with the final results?*

In ** Frame X** is ZYXW, which is WXYZ inverted, this last being the starting point of

**.**

*Frame I*In ** Frame V** is ABDE, which is EDBA inverted, this last being the starting point of

**.**

*Frame II*** Conclusion**:

*Two left and right shifts in sequence will reverse the bits of a number. In this particular case,*

**.**

*B3→B0, B2→B1, B1→B2, B0→B3***Parallel Load (PL) Shifting Registers**

When we said that these circuits are commonly used for converting parallel to serial transmissions, we stated at a particular moment that *“we place another set of 8 bits at the Register and start from the beginning”*.

*Who places them there and how is it done? Surely it’s not us who puts them there one by one?*

Operations like these using these circuits emphasize the need to provide, at any given moment, the the ability to load the ** Shift Register** with a new number to be shifted.

So what we want is a circuit that can perform two types of operations: **Shift** and **Load**.

And that’s the reason why we have the **Parallel Load (PL) Shift Registers**.

Before the input of each of the ** Registry Shift ETLs,** we’ll have a doorman who, before each operation begins, asks you what you want to do. Then, the intended operation is executed, or rather, he performs an operation conditioned by the answer you gave him, a

**.**

*conditional operation**So, what does he ask you?*

*Do you want to keep shifting?* And we answer: *“Yes, we do, (true, so we give him a 1)”* or *“No, we don’t (false, so we give him a 0)”*. And here we have it, a human response, converted into binary, allowing one to choose between two possibilities.

Someone who does something like this is the ** Multiplexer**, our old friend from long ago. And it’s precisely a

**that will be before each**

*MUX***input, in place of the doorman.**

*ETL*Since he has to choose between **Shift** and **Load**, we’ll set at its inputs:

- The output bit of the ETL connected with this one, for the situations where we want to
**Shift**. - The loading bit of a number with the same order as this ETL, for the situations where we want to
**Load**.

In order for it to make a decision, we answer him with a bit called **PL** (*Parallel Load*). It **Shifts** with **PL=1** (*“Yes, it’s true, keep shifting”*), and it **Loads** with **PL=0** (*“No, it’s false, don’t keep shifting”*). This is the ** selection bit** of these 2-to-1

**.**

*MUX*From here on, we’ll call these Registers, ** PL Shift Registers**, PL meaning Parallel Load.

In ** Figure 4, **we display a left

**with**

*PL Shift Register***Shifting**as the chosen option. In

**a left**

*Figure 5,***with**

*PL Shift Register***Loading**as the chosen option, both with a 2 bits width.

In these representations, as well as with the previous definition given to **PL** we define it as ** active at 0**, meaning that the

**executes a**

*MUX***P**

*arallel*

**L**

*oad*when

**PL**is

**0**.

But it doesn’t have to be mandatorily so. It depends greatly on how the connections are made inside the ** MUX**. This is what will define the active state of

**, in each case.**

*PL*In ** Figure 5,** since

**is**

*PL***0**, the parallel load

**and**

*D0***is selected.**

*D1*The **cyan lines** show the path of the memorization (input→output) in ** B1** e

*B0.*The **orange lines** show the inputs ** D0** and

**selected by**

*D1,***in the**

*PL***, which are now at the input of each**

*MUX***prepared to be memorized in the next**

*ETL,***.**

*Clock*In ** Figure 4,** since

**is**

*PL***1**, the shifting of the bits is selected.

The **cyan lines** show the path of the memorization (input→output) in ** B1** and

**.**

*B0*The **orange lines **show the inputs ** S** and

**selected by**

*E,***in the**

*PL***, which are now at the input of each**

*MUX***prepared to be memorized in the next**

*ETL***.**

*Clock*** Figure 6** is a caption of the ETL and MUX, a reduced graphical representation of the one used in

**. The yellow lines represent the input**

*Figure 7***or**

*X0***being selected by**

*X1***in the**

*PL***and set on the output**

*MUX***.**

*Z*In ** Figure 7, **we

__display a left PL Shift Register, executing a Parallel Load, a left shift, and again a Parallel Load. Our goal is to help visualize how the events that activate the different possibilities are linked, and evolve within the MUX and ETL.__

At the MUX *input 1* are the bits to be shifted (selected by PL=1).

At the MUX *input 0* are the bits to be loaded (selected by PL=0).

** Frame I** – Starting situation with the Clock at the down state. The number W,X,Y,Z is at the

*MUX**input 0*, prepared to be loaded into the

**by the**

*Register***. As**

*PL***is**

*PL***0**this is the selected input, and these will be those whose value will be set at the inputs

**.**

*B3,B2,B1 and B0*** Frame II** –

**. The bits W,X,Y,Z at the inputs of the ETL are memorized. The Parallel Load is complete. At the outputs of**

*1st Clock***, we have now W,X,Y,Z.**

*B3,B2,B1 and B0*The bits X,Y,Z are now at *B3,B2,B1**MUX’s**input 1*. The bit A, the new one, is at *B0**MUX’s **input 1*.

Although the new number to be loaded, R,S,T,U, is already at *MUX’s **input 0*, since ** PL **is

**1**, the

*MUX’s**input 1,*X,Y,Z,A,

__is selected to be shifted, and will be set at__

**inputs.**

*B3,B2,B1,B0’s*** Frame III** –

**. The bits X,Y,Z,A at the ETL’s inputs are memorized. The left shift of W,X,Y,Z is executed, being now memorized in**

*2nd Clock***the bits X,Y,Z,A.**

*B3,B2,B1,B0*The bits Y,Z,A are now at *B3,B2,B1**MUX’s**input 1*. The bit __B__, the new one, is at *B0**MUX’s **input 1*.

The new number R,S,T,U to be loaded is still at *MUX’s **input 0*, which will happen at the next ** Clock**, since

**will be**

*PL***0,**and select the

*MUX’s**input 0*

*.*The bits R,S,T,U are set at

**inputs.**

*B3,B2,B1,B0’s*** Frame IV** –

**. The bits R,S,T,U at the ETL’s inputs are memorized, and the bits R,S,T,U are now at**

*3rd Clock***outputs.**

*B3,B2,B1,B0’s*The bits S,T,U are now at *B3,B2,B1**MUX’s**input 1*. The bit A, the new one, is at *B0**MUX’s **input 1*.

The bits S,T,U,A will be at ** B3,B2,B1,B0’s** inputs, since

**will be**

*PL***0,**and select the

*MUX’s**input 1*. Next

**, they will be memorized at**

*Clock***.**

*B3,B2,B1,B0*We will leave it here for now.

Returning to our conversion circuit of a parallel to serial transmission, we mentioned that** “The number to be shifted is loaded, then it is shifted bit by bit to the serial line, and when it’s done shifting, a new number is loaded”.**

*And how does it know when it’s done shifting?*

Through a binary **Counter** circuit, which counts the bits being shifted, and sends out a warning when it is over, giving the signal to load the new number. This is what we will talk about next.